SW-VHDL Co-Verification Environment Using Open Source Tools

The verification of complex digital designs often involves the use of expensive simulators. The present paper proposes an approach to verify a specific family of complex hardware/software systems, whose hardware part, running on an FPGA, communicates with a software counterpart executed on an external processor, such as a user/operator software running on an external PC. The hardware is described in VHDL and the software may be described in any computer language that can be interpreted or compiled into a (Linux) executable file. The presented approach uses open source tools, avoiding expensive license costs and usage restrictions.Unión Europea 68722

Fine-grain circuit hardening through VHDL datatype substitution

Radiation effects can induce, amongst other phenomena, logic errors in digital circuits and systems. These logic errors corrupt the states of the internal memory elements of the circuits and can propagate to the primary outputs, affecting other onboard systems. In order to avoid this, Triple Modular Redundancy is typically used when full robustness against these phenomena is needed. When full triplication of the complete design is not required, selective hardening can be applied to the elements in which a radiation-induced upset is more likely to propagate to the main outputs of the circuit. The present paper describes a new approach for selectively hardening digital electronic circuits by design, which can be applied to digital designs described in the VHDL Hardware Description Language. When the designer changes the datatype of a signal or port to a hardened type, the necessary redundancy is automatically inserted. The automatically hardening features have been compiled into a VHDL package, and have been validated both in simulation and by means of fault injection.Ministerio de Economía y Competitividad ESP2015-68245-C4-2-PComisión Europea ID 687220

A novel co-design approach for soft errors mitigation in embedded systems

Comunicación presentada en the 11th European Conference on Radiation and its Effects on Components and Systems RADECS 2010, Längenfeld, Austria, September 20-24, 2010.A novel proposal to design radiation-tolerant embedded systems combining hardware and software mitigation techniques is presented. Two suites of tools are developed to automatically apply the techniques and to facilitate the trade-offs analyses.This work makes part of RENASER project (ESP2007-65914-C03-03) funded by the 2007 Spain Research National Plan of the Ministry of Science and Education in which context this work has been possible. The work presented here has been carried out thanks to the support of the research project ’Aceleración de algoritmos industriales y de seguridad en entornos críticos mediante hardware’ (GV/2009/098) (Generalitat Valenciana, Spain)

Efficient FPSoC Prototyping of FCS-MPC for Three-Phase Voltage Source Inverters

This work describes an efficient implementation in terms of computation time and resource usage in a Field-Programmable System-On-Chip (FPSoC) of a Finite Control Set Model Predictive Control (FCS-MPC) algorithm. As an example, the FCS-MPC implementation is used for the current reference tracking of a two-level three-phase power converter. The proposed solution is an enabler for using both complex control algorithms and digital controllers for high switching frequency semiconductor technologies. An original HW/SW (hardware and software) system architecture for an FPSoC is designed to take advantage of a modern operating system, while removing time uncertainty in real-time software tasks, and exploiting dedicated FPGA fabric for the most complex computations. In addition, two different architectures for the FPGA-implemented functionality are proposed and compared in order to study the area-speed trade-off. Experimental results show the feasibility of the proposed implementation, which achieves a speed hundreds of times faster than the conventional Digital Signal Processor (DSP)-based control platform.Ministerio de Economía y Competitividad TEC2016-78430-RFondo Nacional de Investigación de Qatar NPRP 9-310-2-13

Sistema para la neuroestimulación

Sistema para la neuroestimulación.Sistema de neuroestimulación comprendiendo una unidad externa de control (110) capaz de transferir energía e instrucciones a un grupo de neuroestimuladores (120,..., 120') implantables en un tejido (100) que constituyen

Application-driven co-design of fault-tolerant industrial systems

This paper presents a novel methodology for the HW/SW co-design of fault tolerant embedded systems that pursues the mitigation of radiation-induced upset events (which are a class of Single Event Effects - SEEs) on critical industrial applications. The proposal combines the flexibility and low cost of Software Implemented Hardware Fault Tolerance (SIHFT) techniques with the high reliability of selective hardware replication. The co-design flow is supported by a hardening platform that comprises an automatic software hardening environment and a hardware tool able to emulate Single Event Upsets (SEUs). As a case study, we selected a soft-micro (PicoBlaze) widely used in FPGA-based industrial systems, and a fault tolerant version of the matrix multiplication algorithm was developed. Using the proposed methodology, the design was guided by the requirements of the application, leading us to explore several trade-offs among reliability, performance and cost.This work makes part of RENASER project (ESP2007-65914-C03-03) funded by the 2007 Research National Plan of the Ministry of Science and Education in which context this work has been possible. The work presented here has been carried out thanks to the support of the research projects ’Aceleración de algoritmos industriales y de seguridad en entornos críticos mediante hardware’ (GV/2009/098) (Generalitat Valenciana) and ’Aceleración hardware de algoritmos industriales para el sector calzado’ (GRE08-P11) (University of Alicante)

Prototipado rápido de sistemas empotrados tolerantes a radiación en FPGA

La creciente capacidad de integración de las FPGA está convirtiendo estos dispositivos en la plataforma preferida para el prototipado rápido de sistemas digitales complejos. Por otro lado, a medida que la tecnología se reduce, cobra importancia la protección de los sistemas frente a los fallos transitorios inducidos por radiación (por ejemplo los Single Event Upsets). En este trabajo se presenta una nueva aproximación de prototipado rápido para el codiseño de sistemas empotrados robustos usando FPGA. Dicha aproximación está soportada por una plataforma de endurecimiento que permite combinar técnicas de tolerancia a fallos basadas en software con técnicas basadas en hardware, obteniendo diferentes configuraciones hardware/software con diferentes niveles de compromiso entre restricciones de diseño, fiabilidad y coste. Como caso de estudio, se han desarrollado varios sistemas empotrados tolerantes a radiación basados en una versión del microprocesador PicoBlaze independiente de tecnología.Este trabajo ha sido financiado por los siguientes proyectos: 'RENASER' (ESP2007-65914-C03-03) del Plan Nacional de Investigación 2007 del Ministerio de Ciencia y Educación; y el proyecto de investigación 'Aceleración de algoritmos industriales y de seguridad en entornos críticos mediante hardware' (GV/2009/098) (Generalitat Valenciana, España)

Mitigación automática de soft-errors en nuevas aplicaciones de los sistemas empotrados

Las crecientes prestaciones de los microprocesadores, derivadas de la miniaturización de las tecnologías electrónicas, están provocando la aparición de nuevas aplicaciones de los sistemas empotrados en todos los ámbitos. Sin embargo, el empleo de las tecnologías nanométricas conlleva una mayor sensibilidad de los procesadores a los fallos transitorios inducidos por radiación (soft-errors). Por tanto, en el desarrollo de las nuevas generaciones de estos sistemas, y no solo en aquellos que deben trabajar en ambientes de alta radiación, la fiabilidad se está convirtiendo en un factor de creciente importancia. En este trabajo se presenta una infraestructura basada en compilador que permite el co-diseño de estos nuevos sistemas donde la tolerancia a fallos es un parámetro tan relevante como lo pueden ser el coste, el consumo o el rendimiento. Las herramientas desarrolladas facilitan la exploración del espacio de diseño existente entre las técnicas de protección puramente hardware y las técnicas basadas en la redundancia del software. De esta forma se obtienen soluciones híbridas con un mejor balance entre los distintos requisitos del diseño, habilitando a los sistemas empotrados para abordar nuevas aplicaciones de seguridad y misión crítica.Este trabajo ha sido financiado por los siguientes proyectos: 'RENASER' (ESP2007-65914-C03-03) del Ministerio de Ciencia y Educación; y 'Aceleración de algoritmos industriales y de seguridad en entornos críticos mediante hardware' (GV/2009/098) (Generalitat Valenciana)

Rapid prototyping of radiation-tolerant embedded systems on FPGA

Technological advances of Field Programmable Gate Array (FPGA) are making that this technology becomes the most preferred platform for the rapid prototyping of highly integrated digital systems. In addition, protection of processor-based systems to mitigate the harmful effects of radiation-induced upset events is gaining importance while technology shrinks. In this context, the main contribution of this work is a novel rapid prototyping approach for the codesign of dependable embedded systems using FPGA. This is supported by a hardening platform that allows combining software-only fault-tolerance techniques with hardware-only approaches, representing several trade-offs among design constraints, reliability and cost. As case study, several radiation-tolerant embedded systems have been developed based on a technology-independent version of the Picoblaze processor.This work was funded by the Ministry of Science and Education in Spain with the RENASER project (ESP2007-65914-C03-03) and the Generalitat Valenciana in Spain with the research project ’Aceleración de algoritmos industriales y de seguridad en entornos críticos mediante hardware’ (GV/2009/098)

A Cross-Disciplinary Outlook of Directions and Challenges in Industrial Electronics

This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/How to build a sustainable society in view of industrial electronics has been discussed from energy, information and communication technologies, cyber-physical systems (CPSs), and other viewpoints. This paper presents a cross-disciplinary view that integrates the fields of human factors, professional education, electronic systems on chip, resilience and security for industrial applications, technology ethics and society, and standards. After explaining the efforts and challenges in these fields, this paper shows a methodology for cross-disciplinary technology that integrates the technical committees in Cluster 4, Industrial Electronics Society. A project, which was launched in March 2022, implements a 'Proof of Concept' trial of the methodology